The present invention relates to Very Large Scale Integrated (VLSI) semiconductor circuit devices and particularly to a structural arrangement and fabrication method for circuit macros for VLSI semiconductor integrated circuits.
VLSI devices are typically formed as circuit chips having a chip image including multiple logic and memory circuits integrally formed on a single semiconductor substrate. The VLSI devices may be formed, for example, by field effect transistor (FET) technique with conventional complementary metal oxide semiconductor (CMSO) technology. Whatever the technology employed, the semiconductor substrate surface is normally covered with a layer of insulation material which serves to protect the underlying semiconductor material and to provide a support for a first level or layer of metalization used for defining conductive lines. A second layer of metalization is carried by a second layer of insulation formed on the first metalization layer and is also used for defining conductive lines usually extending in a different direction. Additional metalization layers may be employed; however, this increases the complexity and two metalization layers are preferred.
VLSI devices are usually designed with a master image computer design system utilizing a library of predesigned functional circuit macros. The term "macro" designates a VLSI circuit arranged for a particular function. A design or chip image for a particular VLSI device is generated utilizing selected ones of the library of predesigned functional macros. An overall chip image is generated by the master image computer design system automatically locating or placing the selected macros on the chip and wiring these macros together to form the desired system.
Predesigned functional macros may include many different integrated circuits variying in complexity from simple inverter circuits to complex memory circuits. Conventionally, functional macros for VLSI devices have been designed with high circuit density in order to minimize semiconductor area and to provide a high performance characteristics for the particular function. This design approach, while providing additional macros with advantages for the intended function, creates serious problems in the layout and design of the overall chip image because the conventional design approach does not effectively facilitate placement and wiring of multiple macros on the chip to provide a desired system.
An example of a design suffering from these disadvantages is found in Balyoz et al., U.S. Pat. No. 4,249,193. This patent discloses a masterslice design technique wherein essentially the entire semiconductor surface area of each chip is utilized to provide cells selectable to be personalized (wired) with one of the semiconductor surface are dedicated for wiring channels. This high density approach to chip image structure decreases flexibility in wiring and macro placement.
Other VLSI chip or masterslice design techniques have made use of wiring bays between groups of cells of the chip array. However, large circuit macros developed in the past for such chips have been structured in such a way that large area blockage of metalization layers has resulted. This has prevented efficient use of the metalization layers and wiring bays. The prior art macro structures of FIGS. 1 and 2 provide examples of the difficulty.
Static random access memories (RAMS) are widely used in VLSI semiconductor devices. Present master image computer design systems generate semiconductor chip designs utilizing multiple versions of RAM macros. FIG. 1 illstrates a block diagram representation of a prior art static RAM macro with a single memory cell array ARRAY, a control section CNTL for address decoding and for providing timing signals to a word line selector section WORD DEC, a bit line selector section BIT SELECT and a sense latch section SENSE LATCHES. The SENSE LATCHES sense and latch read/write R/W data and drive the data outputs. Polysilicon word lines and first level metal bit lines (not shown) are typically used in this type of RAM macro to access the ARRAY.
The entire first metalization level above the semiconductor surface area defining the prior art RAM macro of FIG. 1 is totally used for defining conductive lines for both intra-cell and inter-cell wiring. This total blockage of the first metalization level results in placement limitations of the RAM macro in the chip image because no conductive lines in the first metalization layer are available for other purposes. Further, the number of macro blocks that can be combined to form the chip image is limited by the placement restrictions. Also, an increase in the ARRAY size requires an increased length in the polyisilicon word lines and correspondingly increased resistance. The performance characteristics are degraded due to the resulting increased propagation delay.
FIG. 2 illustrates an alternative prior art RAM arrangement utilized in an attempt reduce the length of the polysilicon word lines and avoid propagation delay problems. This macro includes four distributed memory cell ARRAYS, as shown. The control section CNTL is provided in the center area of the RAM macro and the WORD DEC, BIT SELECT AND BIT LATCHES sections are duplicated for the segmented ARRAYS, and, as compared to the prior art FIG. 1 macro, a larger semiconductor area is required. Like the design of FIG. 1, this design includes polysilicon word lines and first level metal bit lines to access the ARRAYS and results in a first level metal blockage for the RAM macro. Due to the congestion resulting from the centrally provided control section, blockage of a portion of the second level metal also results and wiring and macro placement problems are even more severe.
Many wiring techniques have been developed for the fabrication of semiconducor devices. The following patents disclose examples of such known techniques. None of these prior art approaches provides a structural arrangement complementing wireability of the overall chip image with macros defined to permit wiring through the macro utilizing both first and second wiring lines and enabling a dense macro effectively utilizing semiconductor area and having high performance characteristics.
Japanese specification No. 57-196557 discloses a method to facilitate automation of design of a semiconductor device wherein a semiconductor substrate is divided into sections consisting of sizes (x), (y), functional blocks are formed with the respective sections, and the relative distances between the respective blocks are made to differ by the integer times (x), (y) corresponding to quantities of mutal wirings of the functional blocks.
Japanese specification No. 59-36942 discloses a semiconductor integrated circuit with wiring channels arranged between rows of unit cells and between lines of every fixed number of unit cells.
Warwick, U.S. Pat. No. 4,021,838 discloses a large scale integrated circuit device with a number of integrated circuits or islands 2 arranged in rows and columns and having wiring channels 3 formed between the rows and columns.
Davis, U.S. pat. No. 4,518,874 discloses a bipolar transistor integrated circuit device with a first and second level metal lines connecting the array of bipolar transistors.